I did my undergraduate work at SUNY Buffalo in Electrical Engineering. After that, I managed to get my Masters in Computer Engineering at Santa Clara University .
Currently, I have completed my PhD at the University of Michigan, in the Computer Science and Engineering division in the fall of 2001. My patient advisor was Professor Edward Davidson.
I have developed a framework for x86 performance simulation called Trace Analysis for X86 Interpretation, or TAXI for short. In this infrastructure, I can execute any application that runs on Windows NT (and Windows 95) and then simulate its microarchitecture in order to get estimates on run-time performance, given a specific processor model. Modern x86 processors decompose the x86 instructions into smaller RISC-like instructions called mops - I have developed my own mop mapping for a majority of the x86 instruction set. TAXI not only includes a performance simulator, but also has cache simulator and branch predictor simulator for simplified studies. You can get TAXI here
I worked at Microprocessor Research Lab at Intel, and worked on characterizing natural I/O applications(speech recognition etc.). The previous summer (1997) I worked at Intel Santa Clara on characterizing the performance of Windows NT on Merced. As if I haven't done enough performance analysis, the summer of 1996 saw me doing system-wide (with an emphasis on I/O) performance analysis for Silicon Graphics, Inc.
I am currently working at Sun Microsystems in the Advanced Processor Architectures group doing many different microarchitectural and systems related studies.
S. Vlaovic, E. S. Davidson,
Boosting Trace Cache Performance with NonHead Miss Speculation. 2002 IEEE International Conference on Supercomputing. pp. 179-188, June 2002.E. S. Tam, S. Vlaovic, G. S. Tyson, E. S. Davidson,
Allocation By Conflict: A Simple, Effective Cache Management Scheme. 2001 IEEE International Conference on Computer Design. pp. 133-140, September 2001S. Vlaovic, R. Uhlig. Performance of Natural I/O Applications. 2nd Workshop on Workload Characterization. October 1999.slides.!
S. Vlaovic, S. Arya. System-level Computer Architecture Simulation -- An Experiment report. 1997 IEEE International Performance, Computing, and Communications Conference.
S. Vlaovic. Communication Characterization of a Cray T3D. University of Michigan Techreport CSE-TR-331-97. February 1997.
S. Vlaovic, Q. Li. Redundant linked list based cache coherence protocol. Proceedings of the Conference on Fault-Tolerant Parallel and Distributed Systems 1995. IEEE, Piscataway, NJ, USA. p 43-50; 1995.